Interconnect design considerations for large NUCA caches
نویسندگان
چکیده
منابع مشابه
Way adaptable D-NUCA caches
Non-uniform cache architecture (NUCA) aims to limit the wire-delay problem typical of large on-chip last level caches: by partitioning a large cache into several banks, with the latency of each one depending on its physical location and by employing a scalable on-chip network to interconnect the banks with the cache controller, the average access latency can be reduced with respect to a traditi...
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The on-chip network (NoC) is a fundamental component of Non Uniform Cache Architectures and may significantly affect the performance of the overall system. The analysis described in this work evaluates the performance sensitivity of a single processor system adopting a NUCA L2 cache with respect to some NoC parameters, namely the hop latency and the buffering capacity of routers. The results sh...
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ژورنال
عنوان ژورنال: ACM SIGARCH Computer Architecture News
سال: 2007
ISSN: 0163-5964
DOI: 10.1145/1273440.1250708